1. Field of the Invention
The present invention relates to a symbol timing recovery circuit in a digital demodulator for demodulating received modulated signal by a digital method, and more particularly, to a symbol timing recovery circuit for calculating an accurate symbol rate from a received signal in a variable rate digital demodulator.
2. Description of the Prior Art
In digital communication system, a receiver samples transmitted analog signal in a predetermined sampling clock converting it into a digital signal. A carrier signal having frequency and phase corresponding to modulators used in a transmitter is recovered from the digital signal, and a demodulation is performed by using the recovered carrier signal to recover an original information signal. In a timing recovery circuit, an exact sampling clock, which affects the efficiency of the receiver, is determined.
In digital modems, when sampling is synchronized with data symbol, a feedback loop for controlling the sampling clock by adjusting the phase of local clock or a feedforward loop utilizing regenerated timing wave from the received modulation signal is used, as in an analog modem. When the sampling is not synchronized with the data symbol, namely if the sampling clock is not related to the symbol timing, the timing is controlled by an interpolation. By interpolating between unsynchronized samples, exact strobe values in the modem are generated, similar to the strobe values generated when the sampling is synchronized with the symbol.
FIG. 1 shows a block diagram of a conventional digital timing recovery circuit, that performs the timing recovery using a feedback loop. The digital timing recovery circuit comprises a sampling clock generator 11, a first sampler 12, an interpolator 13, a data filter 14, a timing error detector 15, a loop filter 16, and a controller 17.
In FIG. 1, the sampling clock generator 11 generates a sampling clock in period Ts, in which aliasing does not occur. The first sampler 12 generates a signal X(mTs), which samples a band limited input signal X(t) according to the sampling clock, and outputs it. The interpolator 13 generates and outputs an interpolant y(kTi) for interpolating the signal X(mTs) in interpolation interval Ti. The data filter 14 filters the interpolant y(kTi) to output the final strobe data. The timing error detector 15 detects a timing error from the strobe data. The loop filter 16 removes a noise component of the detected timing error. The controller 17 controls an operation of the interpolator 13 by using the filtered timing error to perform the exact timing recovery.
Referring to FIG. 2, a digitization of the interpolator 13 will be described in detail. FIG. 2 shows a block diagram for explaining an operation of the interpolator 13 in FIG. 1. The interpolator 13 comprises a digital/analog (D/A) converter 21, an interpolating filter 22, and a second sampler 23. In FIG. 2, a sampled signal X(mTs) from a first sampler 12 shown in FIG. 1 is converted into an analog signal x(t) by the D/A converter 21. The analog signal x(t) is filtered by the interpolating filter 22 to generate an interpolated signal y(t). The interpolated signal y(t) is resampled by the second sampler 23 to be outputted as an interpolant y(kTi). Here, the sampling interval of the second sampler 23, namely the interval between the interpolants Ti is provided from the controller 17 in FIG. 1.
An output y(t) from the interpolating filter 22 is expressed by the following expression 1, when an impulse response of the interpolating filter 22 is h.sub.I (t). ##EQU1##
Here, the original signal x(t) does not coincide with the filtered signal y(t). A new sample is obtained by resampling the output y(t) at t=kTi in the second sampler 23, namely interpolant y(kTi), which is expressed by the following expression 2. ##EQU2##
In the above expression 2, if the input signal x(m), the impulse response h.sub.I (t) of the interpolating filter 22, the sampling interval mTs of the first sampler 12, and the sampling interval kTi of the second sampler 23 are known, the interpolant can be calculated digitally from the above expression 2.
To define the variables used in the expression 2, when m is a signal index, a filter index i, basepoint index m.sub.k, fractional interval .mu..sub.k can be calculated by the following expression 3. ##EQU3##
In the above expression 3, int[z] refers to the largest integer not exceeding z, where 0.ltoreq..mu..sub.k &lt;1. Here, the fractional interval .mu..sub.k is very important for adjusting the resampling interval of the interpolator 13, and it is calculated in the controller 17 to be provided to the second sampler 23.
Meanwhile, the variations in the fractional interval .mu..sub.k in respect to the relationship between the intervals Ts and Ti of the first sampler 12 and second sampler 23, respectively, are examined. First, when Ti cannot fractionally reduce with Ts, the fractional interval .mu..sub.k will be irrational and will change for each interpolant. Second, if Ti is assumed very nearly equal to Ts, as if the sampling is nearly synchronized, then the fractional interval .mu..sub.k changes very slowly; if it is quantized, it remains constant over many interpolants. Third, if Ts fractionally reduces with Ti, but not equal Ti, then the fractional interval .mu..sub.k repeats periodically. The expression 2 can be alternatively expressed into the following expression 4 through the substitution by the variables from the expression 3. ##EQU4##
A digital interpolation in a modem can be achieved by the above expression 4. The impulse response value h.sub.I [(i+.mu..sub.k)Ts] of the interpolating filter 22 is a filter tap-coefficient.
The time intervals kTi and (k+1)Ti of the consecutive interpolants is expressed by the following expression 5. EQU kTi=(m.sub.k +.mu..sub.k)Ts Expression 5 EQU (k+1)Ti=(m.sub.k+1 +.mu..sub.k+1)Ts
By the difference of the above equations, the next basepoint index m.sub.k+1 can be expressed by the following expression 6. ##EQU5##
Here, according to the variables in the expression 3, the basepoint indices m.sub.k and m.sub.k+1 are an integer, and the fractional interval is 0.ltoreq..mu..sub.k, .mu..sub.k+1 &lt;1. Accordingly, the basepoint index increment .DELTA.m.sub.k is expressed the following expression 7. ##EQU6##
And, according to the expression 6, the fractional part fp[ ] of the increment is calculated to be zero, hence the next fractional interval .mu..sub.k+1 can be expressed the following expression 8. ##EQU7##
Accordingly, the controller 17 has the structural embodiments for calculating the fraction interval .mu..sub.k and basepoint index increment .DELTA.m.sub.k according to the expressions 7 and 8. Accordingly, the interpolator 13 has the structural embodiments for calculating the interpolants by the expression 4 according to the values provided from the controller 17. By having the structural embodiments of the above controller 17 and interpolator 13, an accurate symbol timing recovery circuit in digital demodulator is provided.